/* <prdef.h>
 *
 *	Processor Register definitions
 */
#ifndef _PRDEF_H
#define _PRDEF_H

#define PR$_KSP		0	/* kernel stack pointer */
#define PR$_ESP		1	/* executive stack pointer */
#define PR$_SSP		2	/* supervisor stack pointer */
#define PR$_USP		3	/* user stack pointer */
#define PR$_ISP		4	/* interrupt stack pointer */
#define PR$_ASN		6	/* address space number register */
#define PR$_SPTEP	7	/* system pte prototype register */
#define PR$_P0BR	8	/* P0 base register */
#define PR$_P0LR	9	/* P0 limit register */
#define PR$_P1BR	10	/* P1 base register */
#define PR$_P1LR	11	/* P1 limit register */
#define PR$_SBR		12	/* system base register */
#define PR$_SLR		13	/* system limit register */
#define PR$_CPUID	14	/* CPU identifier register */
#define PR$_WHAMI	15	/* who am i register */
#define PR$_PCBB	16	/* process control block base */
#define PR$_SCBB	17	/* system control block base */
#define PR$_IPL		18	/* interrupt priority level register */
#define PR$_ASTLVL	19	/* AST level register */
#define PR$_SIRR	20	/* software interrupt request register */
#define PR$_SISR	21	/* software interrupt summary register */
#define PR$_ICCS	24	/* interval clock control status register */
#define PR$_RXCS	32	/* console reciever control status register */
#define PR$_RXDB	33	/* console receiver data buffer register */
#define PR$_TXCS	34	/* console transmit control status register */
#define PR$_TXDB	35	/* console transmit data buffer register */
#define PR$_MAPEN	56	/* mapping enable register */
#define PR$_TBIA	57	/* translation buffer invalidate: all */
#define PR$_TBIS	58	/* TB invalidate: single */
#define PR$_TBIASN	59	/* TB invalidate: address space number */
#define PR$_TBISYS	60	/* TB invalidate: system */
#define PR$_SID		62	/* system identification register */
#define PR$_TBCHK	63	/* translation buffer valid check */
#define PR$_VPSR	144	/* vector processor status register */
#define PR$_VAER	145	/* vector arithmetic exception register */
#define PR$_VMAC	146	/* vector memory access check register */
#define PR$_VTBIA	147	/* vector TB invalidate all */
#define PR$_VSAR	148	/* vector state address register */

/* System ID register CPU types; number assignments are based	*/
/* upon the jumpers read by the console from the MPS backplane	*/
#define PR$_SID_TYP780	1	/* VAX 11/780 */
#define PR$_SID_TYP750	2	/* VAX 11/750 */
#define PR$_SID_TYP730	3	/* VAX 11/730 */
#define PR$_SID_TYP790	4	/* VAX 11/790 */
#define PR$_SID_TYP8SS	5	/* Scorpio for now */
#define PR$_SID_TYP8NN	6	/* Nautilus for now */
#define PR$_SID_TYPUV1	7	/* MicroVAX I */
#define PR$_SID_TYPUV2	8	/* MicroVAX II */
#define PR$_SID_TYP410	8	/* VAXstar */
#define PR$_SID_TYP009	9	/* Virtual VAX */
#define PR$_SID_TYP420	10	/* PVAX */
#define PR$_SID_TYP520	10	/* Cirrus I */
#define PR$_SID_TYP650	10	/* Mayfair */
#define PR$_SID_TYP9CC	10	/* Calypso/XCP */
#define PR$_SID_TYP9CI	10
#define PR$_SID_TYP60	10	/* Firefox */
#define PR$_SID_TYP670	11	/* KA670 (Pele) */
#define PR$_SID_TYP9RR	11	/* XRP */
#define PR$_SID_TYP43	11	/* KA43 (RigelMAX) */
#define PR$_SID_TYP9AQ	14	/* Aquarius */
#define PR$_SID_TYP8PS	17	/* Polarstar */
#define PR$_SID_TYP1202 18	/* Mariah/XMP */
#define PR$_SID_TYP46	18	/* PV-Mariah */
#define PR$_SID_TYP600	19
#define PR$_SID_TYP690	19
#define PR$_SID_TYP700	19
#define PR$_SID_TYP1302 19
#define PR$_SID_TYP49	19
#define PR$_SID_TYP1303 19
#define PR$_SID_TYP660	20	/* KA660 (Spitfire) */
#define PR$_SID_TYP440	20	/* PVAX2 */
#define PR$_SID_TYP4A	20	/* PCVAX */
#define PR$_SID_TYP550	20	/* Cirrus II */
#define PR$_SID_TYP1701 23	/* Laser/Neon */
#define PR$_SID_TYPMAX	23	/* max legal cpu type */
#define PR$_SID_TYP_NOTAVAX 128 /* not a VAX (i.e. Alpha or some such) */
/* chip CPU types */
#define PR$_SID_TYPUV	8	/* MicroVAX chip */
/* MicroVAX chip CPU subtypes */
#define PR$_XSID_UV_UV	0	/* Generic MicroVAX (unused subtype) */
#define PR$_XSID_UV_UV2 1	/* MicroVAX II */
#define PR$_XSID_UV_410 4	/* VAXstar */
#define PR$_SID_TYPCV	10	/* CVAX chip */
/* CVAX chip CPU subtypes */
#define PR$_XSID_CV_CV	0	/* Generic CVAX (unused subtype) */
#define PR$_XSID_CV_650 1	/* Mayfair */
#define PR$_XSID_CV_9CC 2	/* Calypso/XCP */
#define PR$_XSID_CV_60	3	/* Firefox */
#define PR$_XSID_CV_420 4	/* PVAX */
#define PR$_XSID_CV_9CI 5
#define PR$_XSID_CV_520 7	/* CIRRUS I */
#define PR$_SID_TYPRV	11	/* Rigel chip */
/* Rigel chip CPU subtypes */
#define PR$_XSID_RV_RV	0	/* Generic Rigel (unused subtype) */
#define PR$_XSID_RV_670 1	/* KA670 (Pele) */
#define PR$_XSID_RV_9RR 2	/* Calypso/XRP */
#define PR$_XSID_RV_43	4	/* KA43 (RigelMAX) */
#define PR$_SID_TYPV12	18	/* Mariah chip set */
/* Mariah chip CPU subtypes */
#define PR$_XSID_V12_V12  0	/* Generic Mariah (unused subtype) */
#define PR$_XSID_V12_1202 2	/* MARIAH/XMP */
#define PR$_XSID_V12_46 4	/* PVAX- mariah subtype */
#define PR$_SID_TYPV13	19
#define PR$_XSID_V13_V13 0
#define PR$_XSID_V13_690 1
#define PR$_XSID_V13_1302 2
#define PR$_XSID_V13_1303 3
#define PR$_XSID_V13_49 4
#define PR$_XSID_V13_700 5
#define PR$_XSID_V13_600 6
#define PR$_SID_TYPV14	20	/* SOC Chip SID */
/* SOC chip CPU subtypes */
#define PR$_XSID_V14_V14 0	/* unused subtype */
#define PR$_XSID_V14_660 1	/* KA660 (Spitfire) */
#define PR$_XSID_V14_440 4	/* PVAX2 subtype */
#define PR$_XSID_V14_4A 5	/* PCVAX subtype */
#define PR$_XSID_V14_550 7	/* CIRRUS II */
#define PR$_SID_TYPV17	23	/* NVAX+ chip SID */
/* NVAX+ chip CPU subtypes */
#define PR$_XSID_V17_V17	0	/* unused subtype */
#define PR$_XSID_V17_1701	1	/* Laser/Neon */
/* Nautilus CPU subtypes */
#define PR$_XSID_N8800	0	/* VAX 8800 */
#define PR$_XSID_N8700	1	/* VAX 8700 */
#define PR$_XSID_N2	2	/* Undefined Nautilus CPU */
#define PR$_XSID_N3	3	/* Undefined Nautilus CPU */
#define PR$_XSID_N4	4	/* Undefined Nautilus CPU */
#define PR$_XSID_N5	5	/* Undefined Nautilus CPU */
#define PR$_XSID_N8550	6	/* VAX 8550 */
#define PR$_XSID_N8500	7	/* VAX 8500 */
#define PR$_XSID_N8NNN	(-1)	/* Unknown Nautilus CPU */
/* VAX 11/780 IPR's: */
#define PR$_WCSA	44	/* WCS address register */
#define PR$_WCSD	45	/* WCS data register */
#define PR$_SBIFS	48	/* SBI fault status register */
#define PR$_SBIS	49	/* SBI silo register */
#define PR$_SBISC	50	/* SBI comparator register */
#define PR$_SBIMT	51	/* SBI maintenance register */
#define PR$_SBIER	52	/* SBI error register */
#define PR$_SBITA	53	/* SBI timeout address register */
#define PR$_SBIQC	54	/* SBI quadword clear register */
/* end of VAX 11/780-specific IPR's */
/* VAX 11/750 and 11/730 IPR's: */
#define PR$_CMIERR	23	/* CMI error summary register */
#define PR$_CSRS	28	/* console blk store RCV status */
#define PR$_CSRD	29	/* console blk store RCV data */
#define PR$_CSTS	30	/* console blk store XMIT status */
#define PR$_CSTD	31	/* console blk store XMIT data */
#define PR$_TBDR	36	/* TB disable register */
#define PR$_CADR	37	/* cache disable register */
#define PR$_MCESR	38	/* machine check error summary reg */
#define PR$_CAER	39	/* cache error register */
#define PR$_UBRESET	55	/* UNIBUS I/O reset register */
/* end of 11/750 and 11/730 IPR's */
/* VAX 11/790 processor-specific IPRs */
#define PR$_PAMACC	64	/* PAMM access */
#define PR$_PAMLOC	65	/* PAMM location */
#define PR$_CSWP	66	/* cache sweep register */
#define PR$_MDECC	67	/* MBOX data ECC register */
#define PR$_MENA	68	/* MBOX error enable register */
#define PR$_MDCTL	69	/* MBOX data control register */
#define PR$_MCCTL	70	/* MBOX MCC control register */
#define PR$_MERG	71	/* MBOX error generator register */
#define PR$_CRBT	72	/* console reboot */
#define PR$_DFI		73	/* diagnostic fault insertion */
#define PR$_EHSR	74	/* error handling status register */
#define PR$_ACCS790	75	/* accelerator status register */
#define PR$_STXCS	76	/* console storage control reg */
#define PR$_STXDB	77	/* console storage data register */
#define PR$_LSPA	78	/* scratchpad address */
#define PR$_RSPD	79	/* scratchpad data */
/* end of 11/790 processor-specific IPRs */

union prdef {
    struct {
	unsigned pr$v_sid_sn	: 12;	/* serial number field */
	unsigned pr$v_sid_pl	: 3;	/* plant ID */
	unsigned pr$v_sid_eco	: 9;	/* ECO level */
	unsigned pr$v_sid_type	: 8;	/* CPU type code */
    } pr$r_prdef_bits;
    struct {
	unsigned pr$v_fill_xsid_bits : 24; /* CPU-specific XSID bits */
	unsigned pr$v_xsid_type : 8;	/* CPU subtype code */
    } pr$r_prdef_xbits;
};

#endif	/*_PRDEF_H*/