/* <xfdef.h>
 *
 *	DR32 definitions for command table, packets, and characteristics
 */
#ifndef _XFDEF_H
#define _XFDEF_H

/* qio command table offsets */
#define XF$V_IOS_SUCCES 0
#define XF$V_IOS_CMDSTD 1
#define XF$V_IOS_INVPTE 2
#define XF$V_IOS_FREQPK 3
#define XF$V_IOS_DDIDIS 4
#define XF$V_IOS_SLFTST 5
#define XF$V_IOS_RNGERR 6
#define XF$V_IOS_UNQERR 7
#define XF$V_IOS_INVPKT 8
#define XF$V_IOS_FREQMT 9
#define XF$V_IOS_RNDENB 10
#define XF$V_IOS_INVDDI 11
#define XF$V_IOS_LENERR 12
#define XF$V_IOS_DRVABT 13
#define XF$V_IOS_PARERR 14
#define XF$V_IOS_BUSERR 27
#define XF$V_IOS_RDSERR 28
#define XF$V_IOS_WCSPE	29
#define XF$V_IOS_CIPE	30
#define XF$V_IOS_DIPE	31
#define XF$M_IOS_SUCCES (1<<XF$V_IOS_SUCCES)	/* 0x01 */
#define XF$M_IOS_CMDSTD (1<<XF$V_IOS_CMDSTD)	/* 0x02 */
#define XF$M_IOS_INVPTE (1<<XF$V_IOS_INVPTE)	/* 0x04 */
#define XF$M_IOS_FREQPK (1<<XF$V_IOS_FREQPK)	/* 0x08 */
#define XF$M_IOS_DDIDIS (1<<XF$V_IOS_DDIDIS)	/* 0x10 */
#define XF$M_IOS_SLFTST (1<<XF$V_IOS_SLFTST)	/* 0x20 */
#define XF$M_IOS_RNGERR (1<<XF$V_IOS_RNGERR)	/* 0x40 */
#define XF$M_IOS_UNQERR (1<<XF$V_IOS_UNQERR)	/* 0x80 */
#define XF$M_IOS_INVPKT (1<<XF$V_IOS_INVPKT)	/* 0x0100 */
#define XF$M_IOS_FREQMT (1<<XF$V_IOS_FREQMT)	/* 0x0200 */
#define XF$M_IOS_RNDENB (1<<XF$V_IOS_RNDENB)	/* 0x0400 */
#define XF$M_IOS_INVDDI (1<<XF$V_IOS_INVDDI)	/* 0x0800 */
#define XF$M_IOS_LENERR (1<<XF$V_IOS_LENERR)	/* 0x1000 */
#define XF$M_IOS_DRVABT (1<<XF$V_IOS_DRVABT)	/* 0x2000 */
#define XF$M_IOS_PARERR (1<<XF$V_IOS_PARERR)	/* 0x4000 */
#define XF$M_IOS_BUSERR (1<<XF$V_IOS_BUSERR)	/* 0x08000000 */
#define XF$M_IOS_RDSERR (1<<XF$V_IOS_RDSERR)	/* 0x10000000 */
#define XF$M_IOS_WCSPE	(1<<XF$V_IOS_WCSPE)	/* 0x20000000 */
#define XF$M_IOS_CIPE	(1<<XF$V_IOS_CIPE)	/* 0x40000000 */
#define XF$M_IOS_DIPE	(1<<XF$V_IOS_DIPE)	/* 0x80000000 */
#define XF$V_IOS_NEXREG 5
#define XF$V_IOS_LOG	6
#define XF$V_IOS_DDIERR 7
#define XF$M_IOS_NEXREG (1<<XF$V_IOS_NEXREG)	/* 0x20 */
#define XF$M_IOS_LOG	(1<<XF$V_IOS_LOG)	/* 0x40 */
#define XF$M_IOS_DDIERR (1<<XF$V_IOS_DDIERR)	/* 0x80 */
union xfdef {
    struct {
	unsigned xf$v_ios_succes : 1;	/* success */
	unsigned xf$v_ios_cmdstd : 1;	/* command started */
	unsigned xf$v_ios_invpte : 1;	/* invalid PTE */
	unsigned xf$v_ios_freqpk : 1;	/* free queue packet */
	unsigned xf$v_ios_ddidis : 1;	/* DDI disable */
	unsigned xf$v_ios_slftst : 1;	/* self test */
	unsigned xf$v_ios_rngerr : 1;	/* range error */
	unsigned xf$v_ios_unqerr : 1;	/* unaligned queue error */
	unsigned xf$v_ios_invpkt : 1;	/* invalid command packet */
	unsigned xf$v_ios_freqmt : 1;	/* free queue empty */
	unsigned xf$v_ios_rndenb : 1;	/* random enable */
	unsigned xf$v_ios_invddi : 1;	/* invalid DDI command */
	unsigned xf$v_ios_lenerr : 1;	/* length error */
	unsigned xf$v_ios_drvabt : 1;	/* driver abort */
	unsigned xf$v_ios_parerr : 1;	/* parity error (CI or DI) */
	unsigned		 : 1;	/* reserved */
	unsigned xf$v_ios_ddists : 8;	/* DDI status */
	unsigned		 : 3;	/* reserved */
	unsigned xf$v_ios_buserr : 1;	/* bus error */
	unsigned xf$v_ios_rdserr : 1;	/* read data substitute error */
	unsigned xf$v_ios_wcspe  : 1;	/* WCS parity error */
	unsigned xf$v_ios_cipe	 : 1;	/* control interconnect parity error */
	unsigned xf$v_ios_dipe	 : 1;	/* data interconnect parity error */
    } xf$r_xfdef_bits0;
    struct {
	unsigned		 : 5;	/* skip over 5 bits */
	unsigned xf$v_ios_nexreg : 1;	/* non-existent register */
	unsigned xf$v_ios_log	 : 1;	/* log */
	unsigned xf$v_ios_ddierr : 1;	/* error on far-end device */
    } xf$r_xfdef_bits1;
};
/* command packet offsets */
#define XF$V_CMT_SETRTE 0
#define XF$V_CMT_DIPEAB 1
#define XF$M_CMT_SETRTE (1<<XF$V_CMT_SETRTE)	/* 0x01 */
#define XF$M_CMT_DIPEAB (1<<XF$V_CMT_DIPEAB)	/* 0x02 */
#define XF$K_CMT_LENGTH 32	/* length of command table */
#define XF$C_CMT_LENGTH 32
struct xfdef1 {
    unsigned long xf$l_cmt_cblksz;	/* command block size */
    unsigned long xf$l_cmt_cblkad;	/* command block address */
    unsigned long xf$l_cmt_bblksz;	/* buffer block size */
    unsigned long xf$l_cmt_bblkad;	/* buffer block address */
    unsigned long xf$l_cmt_pastad;	/* packet AST address */
    unsigned long xf$l_cmt_pastpm;	/* packet AST address */
    unsigned char xf$b_cmt_rate;	/* data rate */
    union {
	unsigned char xf$b_cmt_flags;	/* flags */
	struct {
	    unsigned xf$v_cmt_setrte : 1; /* set data rate */
	    unsigned xf$v_cmt_dipeab : 1; /* disable parity error abort */
	    unsigned		     : 6;
	} xf$r_cmt_flags_bits;
    } xf$r_cmt_flags_overlay;
    unsigned	: 16;			/* short fill; spare */
    unsigned long xf$l_cmt_gbitad;	/* go bit address */
};
/* function code values */
#define XF$K_PKT_RD	0	/* read */
#define XF$K_PKT_RDCHN	1	/* read chained */
#define XF$K_PKT_WRT	2	/* write */
#define XF$K_PKT_WRTCHN 3	/* write chained */
#define XF$K_PKT_WRTCM	4	/* write control message */
/*  value 5 is reserved */
#define XF$K_PKT_SETTST 6	/* set self test */
#define XF$K_PKT_CLRTST 7	/* clear self test */
#define XF$K_PKT_NOP	8	/* nop */
#define XF$K_PKT_DIAGRI 9	/* diagnostic read internal */
#define XF$K_PKT_DIAGWI 10	/* diagnostic write internal */
#define XF$K_PKT_DIAGRD 11	/* diagnostic read DDI */
#define XF$K_PKT_DIAGWC 12	/* write control message */
#define XF$K_PKT_SETRND 13	/* set random enable */
#define XF$K_PKT_CLRRND 14	/* clear random enable */
#define XF$K_PKT_HALT	15	/* halt */
#define XF$V_PKT_SLNERR 5
#define XF$M_PKT_SLNERR (1<<XF$V_PKT_SLNERR)	/* 0x20 */
#define XF$K_PKT_NOTRAN 0	/* no transmission */
#define XF$K_PKT_CB	1	/* command byte only */
#define XF$K_PKT_CBDM	2	/* command byte and device message */
#define XF$K_PKT_CBDMBC 3	/* cmd. byte, dev. msg, and byte count */
/* values for interrupt control */
#define XF$K_PKT_UNCOND 0	/* unconditional interrupt */
#define XF$K_PKT_TMQMT	1	/* interrupt on term. queue empty */
#define XF$K_PKT_NOINT	2	/* no interrupt */
/* second longword of i/o status block definitions */
#define XF$V_PKT_SUCCES 0
#define XF$V_PKT_CMDSTD 1
#define XF$V_PKT_INVPTE 2
#define XF$V_PKT_FREQPK 3
#define XF$V_PKT_DDIDIS 4
#define XF$V_PKT_SLFTST 5
#define XF$V_PKT_RNGERR 6
#define XF$V_PKT_UNQERR 7
#define XF$V_PKT_INVPKT 8
#define XF$V_PKT_FREQMT 9
#define XF$V_PKT_RNDENB 10
#define XF$V_PKT_INVDDI 11
#define XF$V_PKT_LENERR 12
#define XF$V_PKT_DRVABT 13
#define XF$V_PKT_PARERR 14
#define XF$M_PKT_SUCCES (1<<XF$V_PKT_SUCCES)	/* 0x01 */
#define XF$M_PKT_CMDSTD (1<<XF$V_PKT_CMDSTD)	/* 0x02 */
#define XF$M_PKT_INVPTE (1<<XF$V_PKT_INVPTE)	/* 0x04 */
#define XF$M_PKT_FREQPK (1<<XF$V_PKT_FREQPK)	/* 0x08 */
#define XF$M_PKT_DDIDIS (1<<XF$V_PKT_DDIDIS)	/* 0x10 */
#define XF$M_PKT_SLFTST (1<<XF$V_PKT_SLFTST)	/* 0x20 */
#define XF$M_PKT_RNGERR (1<<XF$V_PKT_RNGERR)	/* 0x40 */
#define XF$M_PKT_UNQERR (1<<XF$V_PKT_UNQERR)	/* 0x80 */
#define XF$M_PKT_INVPKT (1<<XF$V_PKT_INVPKT)	/* 0x0100 */
#define XF$M_PKT_FREQMT (1<<XF$V_PKT_FREQMT)	/* 0x0200 */
#define XF$M_PKT_RNDENB (1<<XF$V_PKT_RNDENB)	/* 0x0400 */
#define XF$M_PKT_INVDDI (1<<XF$V_PKT_INVDDI)	/* 0x0800 */
#define XF$M_PKT_LENERR (1<<XF$V_PKT_LENERR)	/* 0x1000 */
#define XF$M_PKT_DRVABT (1<<XF$V_PKT_DRVABT)	/* 0x2000 */
#define XF$M_PKT_PARERR (1<<XF$V_PKT_PARERR)	/* 0x4000 */
/* values for control interconnect select */
#define XF$V_PKT_NEXREG 5
#define XF$V_PKT_LOG	6
#define XF$V_PKT_DDIERR 7
#define XF$M_PKT_NEXREG (1<<XF$V_PKT_NEXREG)	/* 0x20 */
#define XF$M_PKT_LOG	(1<<XF$V_PKT_LOG)	/* 0x40 */
#define XF$M_PKT_DDIERR (1<<XF$V_PKT_DDIERR)	/* 0x80 */
struct xfdef2 {
    unsigned long xf$l_pkt_flink;	/* forward link */
    unsigned long xf$l_pkt_blink;	/* backward link */
    unsigned char xf$b_pkt_msglen;	/* length of device message area */
    unsigned char xf$b_pkt_loglen;	/* length of log area */
    union {
	unsigned char xf$b_pkt_cmdctl;	/* command control */
	struct {
	    unsigned xf$v_pkt_func   : 4; /* function code */
	    unsigned		     : 4; /* must be zero */
	} xf$r_pkt_cmdctl_bits;
    } xf$r_pkt_cmdctl_overlay;
    union {
	unsigned char xf$b_pkt_pktctl;	/* packet control */
	struct {
	    unsigned		     : 3; /* unused */
	    unsigned xf$v_pkt_cisel  : 2; /* control interconnect select */
	    unsigned xf$v_pkt_slnerr : 1; /* suppress length error */
	    unsigned xf$v_pkt_intctl : 2; /* interrupt control */
	} xf$r_pkt_pktctl_bits;
    } xf$r_pkt_pktctl_overlay;
    unsigned long xf$l_pkt_bfrsiz;	/* buffer size */
    unsigned long xf$l_pkt_bfradr;	/* buffer address */
    unsigned long xf$l_pkt_rmbcnt;	/* residual memory byte count */
    unsigned long xf$l_pkt_rdbcnt;	/* residual DDI byte count */
    union {
	unsigned long xf$l_pkt_dsl;	/* dr32 status longword */
	struct {
	    unsigned xf$v_pkt_succes : 1; /* success */
	    unsigned xf$v_pkt_cmdstd : 1; /* command started */
	    unsigned xf$v_pkt_invpte : 1; /* invalid pte */
	    unsigned xf$v_pkt_freqpk : 1; /* free queue packet */
	    unsigned xf$v_pkt_ddidis : 1; /* DDI disable */
	    unsigned xf$v_pkt_slftst : 1; /* self test */
	    unsigned xf$v_pkt_rngerr : 1; /* range error */
	    unsigned xf$v_pkt_unqerr : 1; /* unaligned queue error */
	    unsigned xf$v_pkt_invpkt : 1; /* invalid command packet */
	    unsigned xf$v_pkt_freqmt : 1; /* free queue empty */
	    unsigned xf$v_pkt_rndenb : 1; /* random enable */
	    unsigned xf$v_pkt_invddi : 1; /* invalid DDI command */
	    unsigned xf$v_pkt_lenerr : 1; /* length error */
	    unsigned xf$v_pkt_drvabt : 1; /* driver abort */
	    unsigned xf$v_pkt_parerr : 1; /* parity error */
	    unsigned		     : 1; /* reserved */
	    unsigned xf$v_pkt_ddists : 8; /* DDI status */
	    unsigned		     : 8; /* reserved */
	} xf$r_pkt_dsl_bits0;
	struct {
	    unsigned		     : 5; /* skip over 5 bits */
	    unsigned xf$v_pkt_nexreg : 1; /* non-existent register */
	    unsigned xf$v_pkt_log    : 1; /* log */
	    unsigned xf$v_pkt_ddierr : 1; /* error on far-end device */
	} xf$r_pkt_dsl_bits1;
    } xf$r_pkt_dsl_overlay;
    unsigned char xf$b_pkt_devmsg;	/* start of device message */
};

#endif	/*_XFDEF_H*/