/* * * Internal processor register definitions for XRV vector processor */ #ifndef _XRVDEF_H #define _XRVDEF_H /* indirect register definitions for XRV vector processor */ #define XRV$_PR_VIADR 157 /* vector indirect address */ #define XRV$_PR_VIDLO 158 /* vector indirect data low */ #define XRV$_PR_VIDHI 159 /* vector indirect data hi */ #define XRV$_VIR_VREG0 0 /* vector register 0 */ #define XRV$_VIR_VREG1 64 /* vector register 1 */ #define XRV$_VIR_VREG2 128 /* vector register 2 */ #define XRV$_VIR_VREG3 192 /* vector register 3 */ #define XRV$_VIR_VREG4 256 /* vector register 4 */ #define XRV$_VIR_VREG5 320 /* vector register 5 */ #define XRV$_VIR_VREG6 384 /* vector register 6 */ #define XRV$_VIR_VREG7 448 /* vector register 7 */ #define XRV$_VIR_VREG8 512 /* vector register 8 */ #define XRV$_VIR_VREG9 576 /* vector register 9 */ #define XRV$_VIR_VREG10 640 /* vector register 10 */ #define XRV$_VIR_VREG11 704 /* vector register 11 */ #define XRV$_VIR_VREG12 768 /* vector register 12 */ #define XRV$_VIR_VREG13 832 /* vector register 13 */ #define XRV$_VIR_VREG14 832 /* vector register 14 */ #define XRV$_VIR_VREG15 960 /* vector register 15 */ #define XRV$_VIR_ALU_OP 1088 /* arithmetic opcode */ #define XRV$_VIR_ALU_SCOP_LO 1096 /* scalar operand LO */ #define XRV$_VIR_ALU_SCOP_HI 1100 /* scalar operand HI */ #define XRV$_VIR_ALU_MASK_LO 1100 /* vector mask LO */ #define XRV$_VIR_ALU_MASK_HI 1104 /* vector mask HI */ #define XRV$_VIR_ALU_EXC 1108 /* ALU exception reg. */ /* location 458 reserved */ #define XRV$_VIR_ALU_DIAG_CTRL 1116 /* diagnostic control */ #define XRV$M_VIR_ALU_DIAG_CTRL_ISL 0x01 #define XRV$M_VIR_ALU_DIAG_CTRL_ISH 0x02 #define XRV$M_VIR_ALU_DIAG_CTRL_IBL 0x04 #define XRV$M_VIR_ALU_DIAG_CTRL_IBH 0x08 #define XRV$M_VIR_ALU_DIAG_CTRL_ICL 0x10 #define XRV$M_VIR_ALU_DIAG_CTRL_ICH 0x20 #define XRV$M_VIR_ALU_DIAG_CTRL_ICI 0x40 #define XRV$M_VIR_ALU_DIAG_CTRL_ABE 0x0100 #define XRV$M_VIR_ALU_DIAG_CTRL_CPE 0x0200 #define XRV$M_VIR_ALU_DIAG_CTRL_IFO 0x0400 #define XRV$_VIR_VERSE_CHIP0 1116 /* verse chip 0 reg. */ #define XRV$_VIR_VERSE_CHIP1 1117 /* verse chip 1 reg. */ #define XRV$_VIR_VERSE_CHIP2 1118 /* verse chip 2 reg. */ #define XRV$_VIR_VERSE_CHIP3 1119 /* verse chip 3 reg. */ #define XRV$_VIR_VCTL_CALU 1152 /* current ALU instr. */ #define XRV$_VIR_VCTL_DALU 1153 /* defered ALU instr. */ #define XRV$_VIR_VCTL_COP_LO 1154 /* current ALU oper. LO */ #define XRV$_VIR_VCTL_COP_HI 1155 /* current ALU oper. HI */ #define XRV$_VIR_VCTL_DOP_LO 1156 /* defered ALU oper. LO */ #define XRV$_VIR_VCTL_DOP_HI 1157 /* defered ALU oper. HI */ #define XRV$_VIR_VCTL_LS 1158 /* load/store instr. */ #define XRV$_VIR_VCTL_STRIDE 1159 /* load/store stride */ #define XRV$_VIR_VCTL_ILL 1160 /* illegal instruction */ #define XRV$_VIR_VCTL_CSR 1161 /* controller Status */ #define XRV$M_VIR_VCTL_CSR_LSS 0x01 #define XRV$M_VIR_VCTL_CSR_LSH 0x02 #define XRV$M_VIR_VCTL_CSR_CDS 0x04 #define XRV$M_VIR_VCTL_CSR_CDH 0x08 #define XRV$M_VIR_VCTL_CSR_VIS 0x10 #define XRV$M_VIR_VCTL_CSR_VIH 0x20 #define XRV$M_VIR_VCTL_CSR_ISE 0x40 #define XRV$M_VIR_VCTL_CSR_STF 0x0200 #define XRV$M_VIR_VCTL_CSR_ETF 0x0400 #define XRV$M_VIR_VCTL_CSR_VHE 0x0800 #define XRV$M_VIR_VCTL_CSR_SEE 0x040000 #define XRV$M_VIR_VCTL_CSR_HEE 0x080000 #define XRV$M_VIR_VCTL_CSR_FRL 0x100000 #define XRV$M_VIR_VCTL_CSR_FRH 0x200000 #define XRV$M_VIR_VCTL_CSR_FDL 0x400000 #define XRV$M_VIR_VCTL_CSR_FDH 0x800000 #define XRV$M_VIR_VCTL_CSR_FSE 0x10000000 #define XRV$M_VIR_VCTL_CSR_FVP 0x20000000 #define XRV$M_VIR_VCTL_CSR_IMP 0x80000000 #define XRV$_VIR_MOD_REV 1162 /* module revision level */ #define XRV$M_VIR_MOD_REV_FIXUP_LS 0x80 #define XRV$_VIR_LSX_P0BR 1280 /* P0 base register */ #define XRV$_VIR_LSX_P0LR 1281 /* P0 length register */ #define XRV$_VIR_LSX_P1BR 1282 /* P1 base register */ #define XRV$_VIR_LSX_P1LR 1283 /* P1 length register */ #define XRV$_VIR_LSX_SBR 1284 /* system base register */ #define XRV$_VIR_LSX_SLR 1285 /* system len. register */ /* 506-507 reserved */ #define XRV$_VIR_LSX_EXC 1288 /* L/S exception reg. */ #define XRV$_VIR_LSX_TBCSR 1289 /* TB control register */ #define XRV$_VIR_LSX_MAPEN 1290 /* map enable register */ #define XRV$_VIR_LSX_TBIA 1291 /* TB invalidate all */ #define XRV$_VIR_LSX_TBIS 1292 /* TB invalidate single */ /* 50d-50f reserved */ #define XRV$_VIR_LSX_MASKLO 1296 /* mask register LO */ #define XRV$_VIR_LSX_MASKHI 1297 /* mask register HI */ #define XRV$_VIR_LSX_STRIDE 1298 /* L/S stride register */ #define XRV$_VIR_LSX_INST 1299 /* L/S instruction */ #define XRV$_VIR_LSX_AGDIAG 1300 /* AG diagnostic reg. */ /* 515-517 reserved */ #define XRV$_VIR_LSX_XBE 1304 /* XMI bus error reg. */ #define XRV$_VIR_LSX_XFADR 1305 /* XMI failed addr reg. */ /* 51a-51f reserved */ #define XRV$_VIR_LSX_CCSR 1312 /* cache control reg. */ /* 521-527 reserved */ #define XRV$M_VIR_LSX_CCSR_ACT 0x01 #define XRV$M_VIR_LSX_CCSR_CPE 0x0200 #define XRV$M_VIR_LSX_CCSR_XSE 0x0400 #define XRV$M_VIR_LSX_CCSR_XHE 0x0800 #define XRV$M_FILL_1 0x7000 #define XRV$M_VIR_LSX_CCSR_CEE 0x8000 #define XRV$M_VIR_LSX_CCSR_SEE 0x010000 #define XRV$M_VIR_LSX_CCSR_ENA 0x020000 #define XRV$M_VIR_LSX_CCSR_HIT 0x040000 #define XRV$M_VIR_LSX_CCSR_FHT 0x080000 #define XRV$M_VIR_LSX_CCSR_FLU 0x100000 #define XRV$M_FILL_2 0x600000 #define XRV$M_VIR_LSX_CCSR_FRL 0x800000 #define XRV$M_VIR_LSX_CCSR_FDL 0x01000000 #define XRV$M_VIR_LSX_CCSR_FDH 0x02000000 #define XRV$M_VIR_LSX_CCSR_IVS 0x04000000 #define XRV$M_VIR_LSX_CCSR_IPS 0x08000000 #define XRV$M_VIR_LSX_CCSR_DXT 0x10000000 #define XRV$M_VIR_LSX_CCSR_IDV 0x20000000 #define XRV$M_VIR_LSX_CCSR_IDP 0x40000000 #define XRV$M_VIR_LSX_CCSR_DTC 0x80000000 #define XRV$_VIR_LSX_WBDIAG 1320 /* WB diagnostic reg */ #define XRV$_VIR_LSX_VMAC1 1321 /* Memory active start */ #define XRV$_VIR_LSX_VMAC2 1322 /* Memory active check */ /* 52b-51f reserved */ #define XRV$_VIR_LSX_TAG 1328 /* TB tag register */ #define XRV$_VIR_LSX_PTE 1329 /* TB PTE register */ /* 532-53f reserved */ union xrvdef { struct { unsigned xrv$v_vir_alu_diag_ctrl_isl : 1; /* invert scalar operand parity low */ unsigned xrv$v_vir_alu_diag_ctrl_ish : 1; /* invert scalar operand parity high */ unsigned xrv$v_vir_alu_diag_ctrl_ibl : 1; /* invert B parity low */ unsigned xrv$v_vir_alu_diag_ctrl_ibh : 1; /* invert B parity high */ unsigned xrv$v_vir_alu_diag_ctrl_icl : 1; /* invert CD bus parity low */ unsigned xrv$v_vir_alu_diag_ctrl_ich : 1; /* invert CD bus parity high */ unsigned xrv$v_vir_alu_diag_ctrl_ici : 1; /* invert internally generated CP parity */ unsigned : 1; unsigned xrv$v_vir_alu_diag_ctrl_abe : 1; /* AB parity error */ unsigned xrv$v_vir_alu_diag_ctrl_cpe : 1; /* C bus parity error */ unsigned xrv$v_vir_alu_diag_ctrl_ifo : 1; /* illegal FAVOR opcode */ unsigned : 21; } xrvr_xrv_vir_alu_diag_ctrl_bits; struct { unsigned xrv$v_vir_vctl_csr_lss : 1; /* load store chip soft error */ unsigned xrv$v_vir_vctl_csr_lsh : 1; /* load store chip hard error */ unsigned xrv$v_vir_vctl_csr_cds : 1; /* soft internal bus parity error */ unsigned xrv$v_vir_vctl_csr_cdh : 1; /* hard internal bus parity error */ unsigned xrv$v_vir_vctl_csr_vis : 1; /* VIB bus soft error */ unsigned xrv$v_vir_vctl_csr_vih : 1; /* VIB* bus hard error */ unsigned xrv$v_vir_vctl_csr_ise : 1; /* illegal sequence error */ unsigned xrv$v_vir_vctl_csr_mcode : 2; /* machine check code */ unsigned xrv$v_vir_vctl_csr_stf : 1; /* self test failed */ unsigned xrv$v_vir_vctl_csr_etf : 1; /* extended test failed */ unsigned xrv$v_vir_vctl_csr_vhe : 1; /* verse hard error */ unsigned : 6; unsigned xrv$v_vir_vctl_csr_see : 1; /* soft error enable */ unsigned xrv$v_vir_vctl_csr_hee : 1; /* hard error enable */ unsigned xrv$v_vir_vctl_csr_frl : 1; /* force bad RFA low parity */ unsigned xrv$v_vir_vctl_csr_frh : 1; /* force bad RFA high parity */ unsigned xrv$v_vir_vctl_csr_fdl : 1; /* force bad CD bus low data parity */ unsigned xrv$v_vir_vctl_csr_fdh : 1; /* force bad CD bus high data parity */ unsigned xrv$v_vir_vctl_csr_cmod: 2; /* current mode during error */ unsigned : 2; unsigned xrv$v_vir_vctl_csr_fse : 1; /* force soft error */ unsigned xrv$v_vir_vctl_csr_fvp : 1; /* force bad VIB bus parity data parity */ unsigned : 1; unsigned xrv$v_vir_vctl_csr_imp : 1; /* implementation specific error */ } xrvr_xrv_vir_vctl_csr_bits; struct { unsigned xrv$v_vir_mod_rev_revision : 7; /* module revision */ unsigned xrv$v_vir_mod_rev_fixup_ls : 1; /* load store fixup trigger */ unsigned : 24; } xrvr_xrv_vir_mod_rev_bits; struct { unsigned xrv$v_vir_lsx_ccsr_act : 1; /* memory activity */ unsigned xrv$v_vir_lsx_ccsr_lsxrev : 4; /* load store chip revision */ unsigned xrv$v_vir_lsx_ccsr_nodeid : 4; /* XMI node id */ unsigned xrv$v_vir_lsx_ccsr_cpe : 1; /* cache parity error */ unsigned xrv$v_vir_lsx_ccsr_xse : 1; /* XMI interface soft error */ unsigned xrv$v_vir_lsx_ccsr_xhe : 1; /* XMI interface hard error */ unsigned : 3; unsigned xrv$v_vir_lsx_ccsr_cee : 1; /* cache error enable */ unsigned xrv$v_vir_lsx_ccsr_see : 1; /* soft error enable */ unsigned xrv$v_vir_lsx_ccsr_ena : 1; /* cache enable */ unsigned xrv$v_vir_lsx_ccsr_hit : 1; /* cache hit */ unsigned xrv$v_vir_lsx_ccsr_fht : 1; /* force cache hit */ unsigned xrv$v_vir_lsx_ccsr_flu : 1; /* invalidate cache */ unsigned : 2; unsigned xrv$v_vir_lsx_ccsr_frl : 1; /* force bad low RFA parity */ unsigned xrv$v_vir_lsx_ccsr_fdl : 1; /* force bad low data parity */ unsigned xrv$v_vir_lsx_ccsr_fdh : 1; /* force bad high data parity */ unsigned xrv$v_vir_lsx_ccsr_ivs : 1; /* invert valid bit sense */ unsigned xrv$v_vir_lsx_ccsr_ips : 1; /* invert parity sense */ unsigned xrv$v_vir_lsx_ccsr_dxt : 1; /* disable XMI transactions */ unsigned xrv$v_vir_lsx_ccsr_idv : 1; /* invert duplicate tag valid sense */ unsigned xrv$v_vir_lsx_ccsr_idp : 1; /* invert duplicate tag parity sense */ unsigned xrv$v_vir_lsx_ccsr_dtc : 1; /* duplicate tag check */ } xrvr_xrv_vir_lsx_ccsr_bits; }; #endif /*_XRVDEF_H*/